Inferno Port to The Cell BE
So, this is where I’ll be posting bits of information about what’s happening in the Cell BE port. The current code base is built on the PPC440 port, which is used in IBM’s Blue Gene. Currently, most attention is given to MMU code, which is substantially different from PPC440. The kernel now boots on IBM’s systemsim simulator, but only to panic after mapping the first user page. I noticed that the number of kernel pages is being calculated differently in several locations, and this may be leading to inconsistency. I’m almost sure that this is one of the problems because I noticed that the kernel is reporting the wrong amount of physical memory. I hope to be able to figure out the problem soon. Also, to make mapping of kernel pages easier, one of the four ways of the TLB is being monopolized by kpages alone, which has to change.
The next step I guess would be enabling the second PPU thread, as we’re only using one. Then it might be a suitable time to turn our attention to the SPUs, which should be interesting.
Till the next time…